Optimizing the Time-Quality-Cost Equation, SEMI EMTC 2006 
Published 4-Apr-2006, by Colin Ritchie, Ric Dokken, et al., at SEMICON Europa, Munich, Germany.  View Abstract

Scan Debug and Diagnosis, SWDFT 2005 
Published May-2005, by Alfred L. Crouch, et al., at SWDFT, May 2005.  View Abstract

Future Trends in Test, ITC 2004  
Published Oct-2004 by Al Crouch, at the International Test Conference, 2004, ITC 2004 Pages 698-703.  View Abstract

Wafer Level Package Test Strategies, IWLPC 2004 
Published 2004 by Al Crouch and Paul Sakamoto, at the International Wafer-Level Packaging Conference, San Jose, CA, October 10-12, 2004.  View Abstract

Testing Parametric Cores: A Multilayer Test Program to Improve and Automate the EDA-ATE Link 
Published 11-Apr-2005, by Simondavide Tritto, et al., at the 8th European Manufacturing Test Conference (EMTC), Munich, Germany, 11 April 2005.  View Abstract

Extending STIL 1450 Standard for Test Program Flow 
Published 28-Oct-2004, by David Dowding, et al., at the Test Conference, 2004, Proceedings, International, Oct. 26-28, 2004, Page(s): 423 - 431.  View Abstract

Collaboration Through Industry Standards for Manufacturing Success 
Published 16-Jul-2004, by David Dowding, et al., at the Electronics Manufacturing Technology Symposium, 2004, IEEE/CPMT/SEMI 29th International, July 14-16, 2004, Pages: 259 - 262.  View Abstract

A System Perspective on DFT 
Published 24-Oct-2003, by Wilhelm Radermacher, Keynote speech at ASIC, 2003, Proceedings, 5th International Conference on Volume 2, 21-24 October, 2003, Pages: a15 - a15.  View Abstract

Defect Coverage of Boundary-Scan Tests: What Does it Mean when a Boundary-Scan Lestpasses? 
Published 02-Oct-2003, by Kenneth P. Parker, at the Test Conference, 2003, Proceedings, ITC 2003, International, Volume 2, Sept. 3 - Oct. 2, 2003, Pages: 181 - 189.  View Abstract

Future ATE: Perspectives & Requirements 
Published 02-Oct-2003, by Fidel Muradali at the Test Conference, 2003, Proceedings, ITC 2003, International, Volume 1, Sept. 30 - Oct. 2, 2003, Pages: 1297 - 1297.  View Abstract

ATPG Padding and ATE Vector Repeat per Port for Reducing Test Data Volume 
Published 02-Oct-2003, by Domenico Chindamo, et al., at the Test Conference, 2003, Proceedings, ITC 2003, International, Vol.1, Iss., Sept. 30-Oct. 2, 2003, Pages: 1069- 1078.  View Abstract

Leveraging P1450.6 for Faster Production Test Development 
Published 28-May-2003, by Domenico Chindamo, et al., at the European Manufacturing Test Conference, Maastricht, The Netherlands, 25 - 28 May 2003.  View Abstract

Test Vector Compression Using EDA-ATE Synergies 
Published 02-May-2002, by Ajay Khoche, et al., at the VLSI Test Symposium, 2002, (VTS 2002), 28 Apr - 2 May, 2002, Proceedings 20th IEEE, Vol., Iss., 2002, Pages: 97 - 102.  View Abstract

An Evolution to a DFT-Centric Test Paradigm that Scales with Technology Progress 
Published 01-Jun-2001, by Wilhelm Radermacher and Jochen Rivoir, at the European Test Workshop, May 29 - June 1, 2001, Stockholm, Sweden.   View Abstract

Characterization and Focus Calibration of ATE Systems for High-Speed Digital Applications 
Published February 2009, by Jose Moreira and Bernhard Roth, DesignCon 2009, Feb. 2-5, Santa Clara, CA.   View Abstract

GDDR5 Training – Challenges and Solutions for ATE-based test  
Published November 2008, by Hubert Werkmann, Kim Dong-Myong and Shinji Fujita, IEEE Asian Test Symposium 2008, Nov. 24-27, Sapporo JP.   View Abstract

Crosstalk at the BGA Ball-Out Presents Significant Challenges for Multi-Gigabit ATE At-Speed Testing  
Published December 9th - 12th, 2008, Heidi Barnes,et al., 72nd ARFTG Microwave Measurement Symposium, Portland, Oregon, Proceedings.   View Abstract

Measurement-based Modeling for High Speed Semiconductor Test Interface Boards  
Published November 30, 2007, Heidi Barnes, Jose Moreira, Don Faller, ARFTG 70th Microwave Measurement Symposium, Proceedings, November 27 - 30th, 2007.   View Abstract

At-Speed Loopback Testing: Strategies and Techniques  
Published October 30, 2008, by Jose Moreira, Joerg-Walter Mohr, Roger Nettles, at ATE Vision 2020, October 30-31 2008, Santa Clara, CA.   View Abstract

Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment  
Published October 2008, by Jose Moreira, et al., proceedings, ITC 2008, Paper L2.3, 1-4244-1128-9/07/   View Abstract

The Importance of Measurement Verification for Accurate Uncertainty Analysis of Network Analyzer PCB TRL Calibration Standards  
Published June 2008, Heidi Barnes, et al., International Microwave Symposium, Atlanta, Georgia, Proceedings, June 15-20, 2008.  View Abstract

ATE Interconnect Performance to 43 Gbps Using Advanced PCB Materials  
Published February 2008, by Heidi Barnes, et al., at Designcon 2008,Santa Clara, CA, 4 -7 February 2008.   View Abstract

The Physical Realities of Cascading S-Parameters for Full-Path Simulations  
Published February 2008, by Heidi Barnes, at the Computer Simulation Technology North American User's Forum, February 4, 2008.   View Abstract

Performance at the DUT: Techniques for Evaluating the at the Device Under Test Socket  
Published February 2008, by Heidi Barnes, et al., at Designcon 2008,Santa Clara, CA, 4 -7 February 2008.   View Abstract

Analyzing and Addressing the Impact of Test Fixture Relays for Multi-Gigabit ATE I/O Characterization Applications 
Published by Jose Moreira, Heidi Barnes, Guenter Hoersch; 1-4244-1128-9/07/ ©2007 IEEE  View Abstract

Passive Equalization of DUT Loadboards for High-Speed Digital Application 
Published December 2007, Jose Moreira, Verigy; Michael Howieson, Mark Broman, Thin Film Technologies, at Voice 2007  View Abstract

Efficient Data Collection for Volume Diagnosis on V93000 
Published 26-October-2007, by Michael Braun, et al. at the 1st IEEE International Workshop on Automated Test Equipment: Vision ATE 2020 - 10/26/2007.  View Abstract

Beyond 10Gb/s? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment 
Published 25-October-2007, by Jose Moreira, et al. at the 1st IEEE International Workshop on Automated Test Equipment: Vision ATE 2020 - 10/25/2007.  View Abstract

Influence of Dielectric Materials on ATE Test Fixtures for High-Speed Digital Applications 
Published 28-July-2007, by Jose Moreira, et al. at the Sixth International Kharkov Symposium on Physics and Engineering of Microwave, Millimeter and Submillimeter Waves (MSMW’07).  View Abstract

Addressing the Broadband Crosstalk Challenges of Pogo Pin Type Interfaces for High-Density High-Speed Digital Apps 
Published 7-June-2007, by Bela B. Szendrenyi, et al. at the IEEE MTT-S 2007 International Microwave Symposium, 7 June 2007.  View Abstract

Differential PCB Structures using Measured TRL Calibration and Simulated Structure De-Embedding 
Published 31-January-2007, by Heidi Barnes, et al., at DesignCon 2007 on 31 January 2007.  View Abstract

Development of a Pogo Pin Assembly and Via Design for Multi-Gigabit Interfaces on Automated Test Equipment 
Published 13-December-2006, by Heidi Barnes, et al. at the Asia-Pacific Microwave Conference 2006, 13 December 2006.  View Abstract

Passive Equalization of Test Fixtures for High-Speed Digital Measurements with Automated Test Equipment 
Published 20-Nov-2006, by Jose Moreira, et al. at the 2006 International Design and Test Workshop, November 19-20, 2006.  View Abstract

Parametric Testing of a 10Gbs I/O Cell in Production through a Parametric Loopback Approach with Retiming 
Published 20-Nov-2006, by Jose Moreira, et al. at the 2006 International Design and Test Workshop, November 19-20, 2006.  View Abstract

Comparison of Measurement Method by Analog and Digital Resource for High Speed Serial Interface 
Published 09-Dec-2005, by Takashi Ito at the Semi Technology Symposium in Semicon Japan 2005, Proceedings, 7-9 December 2005.  View Abstract

A Test Case for 3Gbps Serial Attached SCSI (SAS) 
Published 10-Nov-2005, by J. Liu, et al. at the Test Conference, 2005, Proceedings, International, 8-10 Nov. 2005.  View Abstract

Addressing the Challenges of Implementing an At-Speed Production Test-Cell for 10Gb/s Wafer Probing 
Published 2-Feb-2005, by Jose Moreira, et al. at DesignCon 2005, 31-Jan - 2-Feb, 2005.  View Abstract

A Model-Based Test Approach for Testing High Speed PLLs & Phase Regulation Circuitry in SOC Devices 
Published 28-Oct-2004, by Bernd Laquai at the Test Conference, 2004, Proceedings, International, 26-28 Oct. 2004, Pages: 764- 772.  View Abstract

Integrating Boundary Scan into Multi-GHz I/O Circuitry 
Published 28-Oct-2004, by Jeff Rearick, et al. at the Test Conference, 2004, Proceedings, International, 26-28 Oct. 2004, Pages: 560 - 566.  View Abstract

Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE 
Published 28-Oct-2004, by Guido Schulze, et al. at the Test Conference, 2004, Proceedings, International 2004, Pages: 1303 - 1312.  View Abstract

Divide and Conquer Based Fast Shmoo Algorithms 
Published 28-Oct-2004, by P. Patten at the Test Conference, 2004, Proceedings, International, 26-28 Oct. 2004, Pages: 197 - 202.  View Abstract

Testing High Speed Serial IO Interfaces Based on Spectral Jitter Decomposition 
Published 14-Oct-2004, by Rainer Plitschka and Bernd Laquai at DesignCon 2004, 11-14 October 2004.  View Abstract

Enabling the PCI Express(TM) Ramp -- ATE Based Testing of PCI Express Architecture 
Published 01-Aug-2004, by Hubert Werkmann at Euro DesignCon 2004, 11-14 October 2004.

Sequential Bayesian Bit Error Rate Measurement 
Published 01-Aug-2004, by Lee Barford at the Instrumentation and Measurement Technology Conference, IEEE Transactions on Volume 53, Issue 4, Aug. 2004, Pages: 947 - 954.  View Abstract

Serial ATA Testing with Analog Tester Resources 
Published 16-Jul-2004, by Hideo Okawara at the Electronics Manufacturing Technology Symposium, 2004, IEEE/CPMT/SEMI 29th International, July 14-16, 2004, Pages: 212- 217.  View Abstract

Delay Defect Screening Using Process Monitor Structures 
Published 29-Apr-2004, by Erik Volkerink at the VLSI Test Symposium, 2004, Proceedings, 22nd IEEE, 25-29 April 2004, Pages: 43 - 48.  View Abstract

Managing the Multi-Gbit/s Test Challenges 
Published 02-Oct-2003 by Ulrich Schoettmer and Bernd Laquai at the Test Conference, 2003, Proceedings, ITC 2003, International, Volume 1, Sept. 30-Oct. 2, 2003, Page(s): 1310 - 1310.  View Abstract

First IC Validation of IEEE Std. 1149.6 
Published 02-Oct-2003 by Suzette Vandivier, et al. at the Test Conference, 2003, Proceedings, ITC 2003, International Volume 2, Sept. 30-Oct. 2, 2003, Pages: 79 - 86.  View Abstract

Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture 
Published 01-May-2003, by Jeff Rearick at the VLSI Test Symposium, 2003, Proceedings, 21st, 27 April-1 May 2003, Pages: 15 - 21.   View Abstract

A Method to Generate a Very Low Distortion, High Sine Waveform Using an AWG  
Published October 28, 2008, by Akinori Maeda, International Test Conference 2008, Paper 22.1 1-4244-4203-0/08/.  View Abstract

Real-Time Signal Processing ― A New PLL Test Approach 
Published 28-Nov-2007, by Hideo Okawara, at International Test Conference 2007, November 28-29, 2007, Paper 16.1, 1-4244-1128-9/07.   View Abstract

Comparison of Measurement Method by Analog and Digital Resource for High Speed Serial Interface 
Published 09-Dec-2005, by Takashi Ito at the Semi Technology Symposium in Semicon Japan 2005, Proceedings, 7-9 December 2005.  View Abstract


Analysis of Pseudo-Interleaving AWG 
Published 08-Nov-2005, by Hideo Okawara at the Test Conference 2005, Proceedings, International, 8-Nov. 2005, Pages: 1174 - 1181.  View Abstract


Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel 
Published 17-Nov-2004, by Jochen Rivoir at the Test Symposium, 2004, 13th Asian, Vol., Iss., 15-17 Nov. 2004, Pages: 290 - 295.  View Abstract


Precise Pulse Width Measurement in Write Pre-Compensation Test 
Published 28-Oct-2004, by Hideo Okawara at the Test Conference, 2004, Proceedings, International, 26-28 Oct. 2004, Pages: 972 - 979.  View Abstract


Single SOC Test Challenge for Blu-Ray DVD 
Published 06-May-2004, by Don Blair and Keita Gunji at Semicon Singapore, May 4-6, 2004.  View Abstract


Mixed-Signal LSI Relationship Among Measurement Accuracy, Yield, and Test Time 
Published 25-Apr-2004, by Hideo Kohinata, et al. at the Workshop on Current and Defect Based Testing, 2004, DBT 2004, Proceedings, 2004 IEEE International Workshop on 25 April 2004, Pages: 43 - 45.  View Abstract


Practical Design Methodologies that Enable Concurrent Testability of Multiple Analog and Digital Modules in SOC Devices and Provide Significant Reusability of ATE Test Vendors 
Published 20-Apr-2004, by Jeff Brenner at Semicon Europa EMTC in Munich on April 20, 2004.


Technical and Economic Requirements of Integrated SOC Testing 
Published 18-Jul-2003, by Don W. Blair at the Electronics Manufacturing Technology Symposium, IEMT 2003, IEEE/CPMT/SEMI 28th International, 16-18 July 2003, Pages: 215 - 219.  View Abstract

Frequency/Phase Movement Analysis by Orthogonal Demodulation 
Published 10-Oct-2002, by Hideo Okawara at the Test Conference, 2002, Proceedings, International, 8-10 Oct. 2002.   View Abstract

DUT Loadboard Layout for Multi-Gigabit Bi-Directional Interfaces 
Published December 2007, Jose Moreira, Heidi Barnes, Hubert Werkmann, Verigy, at Voice 2007  View Abstract

PCB Loadboard Design Challenges for Multi-Gigabit Devices in Automated Test Applications 
Published by Jose Moria, et al. at DesignCon 2006.  View Abstract

Liquid-cooling on the Verigy V93000 SOC Series - The Advantages for Testing and Cost of Test 
Published 16-Mar-2007, Revised in 2007 by Joe Kelly.  View Abstract

Optimizing the Whole Test System to Achieve Optimal Yields and Lowest Test Costs 
Published 16-Jul-2004, by Dave Haupt at the Electronics Manufacturing Technology Symposium, 2004, IEEE/CPMT/SEMI 29th International, July 14-16, 2004, Pages: 282 - 294.  View Abstract

Future ATE for System on a Chip... Some Perspectives 
Published 02-Oct-2003, by Tom Newsom at the Test Conference, 2003, Proceedings, ITC 2003, International, Vol.1, Iss., Sept. 30-Oct. 2, 2003, Page(s): 1301- 1301.  View Abstract

Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings  
Published 01-Oct-2003, by Peter C. Maxwell at Design & Test of Computers, IEEE Volume: 20, Issue: 5, Sept.-Oct. 2003, Pages: 84 - 89.   View Abstract

Production Test Places New Requirements on Noise Figure Measurement Techniques 
Published 23-Mar-2007, Revised in 2007 by Joe Kelly.  View Abstract

Innovative Technique for Testing Wide Bandwidth Frequency Response 
Published 17-Nov-2004, by Frank Goh, et al. at the Wireless Broadband Forum 2004, 16-17 November 2004.  View Abstract

Using a Digital Channel of a Test System as an Analog Reference for Wireless SOC Testing 
Published 16-Jul-2004, by Roger McAleenan and Joe Kelly at the Electronics Manufacturing Technology Symposium, 2004, IEEE/CPMT/SEMI 29th International, 14-16 July 2004, Pages: 194 - 197.  View Abstract

Integrated Cellular Transceivers: Challenging Traditional Test Philosophies 
Published 18-Jul-2003, by Edwin Lowery at the Electronics Manufacturing Technology Symposium, 2003, IEMT 2003, IEEE/CPMT/SEMI 28th International, 16-18 July 2003, Pages: 427 - 436.  View Abstract

Measurement Challenges for On-Wafer RF-SOC Test 
Published 18-Jul-2002, by Wai Yuen Lau at the Electronics Manufacturing Technology Symposium, 2002, IEMT 2002, 27th Annual IEEE/SEMI International, 17-18 July 2002, Pages: 353 - 359.   View Abstract