Published 2004

Abstract
The rapid spread of wafer level packaging (WLP), and other hybrid semiconductor packaging, has brought new demands upon the semiconductor component test flow. In the past, device test quality was assured in multiple test phases that occurred both post fabrication (wafer sort) and post assembly (final or package test). This legacy test process was very adequate to the devices of the time, which were generally individual silicon chips wire bonded to metal lead frames. The wafer sort test was run at reduced specifications, often with a reduced pattern set or set of tests. The post assembly tests were then run at full performance, or as close as the available test equipment would allow, to simulate functional operation of the device. Depending on the device type and technology, there were often more than one test socketing at each of the aforementioned stages.