Testing in the nanoelectronics age challenges conventional wisdom about microelectronics testing. In the sub-micron world, new failure modes can only be understood with new forms of testing. Far beyond simply determining pass/fail, back-end testing must also provide insight for improving designs. More must be accomplished while continuing to drive down overall cost-of-test.
Testing nanoelectronics involves new challenges. Process nodes at 65nm and smaller include new fail mechanisms, such as transition and bridging faults, design process interaction and inter- and intra-die variations. The challenge is made greater by growing scan vector volumes, plus more use of on-chip compression and BIST structures. Attention needs to be put on greater measurement accuracy, such as the lower voltages and higher speeds typical with smaller geometries, in addition to the integration of performance analog and DC.
With initial yield figures in nanoelectronics dropping, accurate measurements take on new importance for closing the loop between test and design to enable rapid yield learning and improvement. Particularly with wafer probe and final test, which has traditionally focused on pass/fail, ongoing parametric and diagnostic data collection can provide valuable device performance insights to benefit new designs.
Meanwhile, relentless price erosion translates into cost-of-test pressure. The volume diagnostics described above increase the test time necessary for diagnostic data collection. Therefore, driving down cost-of-test requires optimal throughput. Manufacturers must take advantage of continuous changes in test methodologies, such as more multi-site, reduced pin count access, and loop-back methodologies, while reducing data collection to only the most relevant information.
In short, the ideal testing solution must strike the perfect balance between insight learned and manufacturing efficiency achieved.
The Verigy V93000 Nanoelectronics Digital Solution is a low-risk, economical test solution that accelerates time-to-market by targeting fail mechanisms that become business-critical at 65nm and smaller. It improves yields by targeting fail mechanisms that become business-critical at 65nm and smaller.