Mobility, interconnectivity and multimedia are driving ICs toward smaller, ultra-thin packages of stacked chips with more functionality and greater performance. A higher level of chip integration when combined with today’s smaller form factors make it increasingly challenging to perform final package test effectively and economically. To ensure quality, maximize yield and lower costs, the components of these highly integrated system-in-packages (SIPs) often require known-good die (KGD) reliability before entering the packaging step. Increasingly these components are being packaged and tested at the wafer level, commonly referred to as wafer level chip scale packages (WLCSPs).

By conducting at wafer stage the testing normally conducted after devices are packaged, many efficiencies are achieved that lower cost of test. Multi-site testing coupled with reduced indexing and faster test times boosts throughput. Failed die can be marked for removal and sometimes repaired ensuring fewer bad die make it to final packaging, increasing yields. In the case of new products and during process ramp, full test results at wafer provide faster feedback to designers and fabricators. The design effort and hardware cost of test setups can be shared between test points, reduced or even eliminated.

To take advantage of these process opportunities, chip designers and manufacturers seek ways to achieve the highest performance test at wafer probe. To date, manufacturers have struggled to get the test performance needed to fully perform functional testing directly on the wafer. The chief obstacle, among other factors, has been the loss in signal integrity caused by the distance between the tester pin electronics and the probe tip.

Verigy’s V93000 Direct-Probe^TM solution reduces the length and number of signal path transitions between tester and probe card enabling the industry's highest test performance to now be brought to digital, mixed-signal and RF devices at wafer probe.