SmartRA

Scalable, flexible and cost-effective RA solution for DRAM at wafer sort

SmartRA, an option for the V6000 WS, provides the performance needed to conduct redundancy analysis on DRAM devices, thereby allowing manufacturers to achieve their throughput and yield goals for wafer sort.

SmartRA provides flexible performance for a wide variety of cases that a manufacturer might encounter, including low or high test frequencies, and low or high levels of complexity with redundancy design. SmartRA eliminates the possibility of timeouts (during which RA time exceeds the shorter pattern time made possible by the V6000's parallelism), thereby maintaining high throughput and yields. SmartRA's open architecture makes it possible to use either Verigy RA algorithms or algorithms that customers have defined themselves; customers need not be tied to proprietary software architectures. The open architecture also uses off-the-shelf high-performance blade servers, enabling customers to add only the performance required for their immediate needs, without impacting the test cell footprint, and do so at minimal cost. The testing solution will remain viable and cost-effective into the future.

Ample and scalable performance for wide range of test cases
A solution for all cases that a manufacturer might encounter, SmartRA handles low or high test frequencies, and low or high levels of complexity with redundancy design.

Here's why greater performance is so important, specifically with RA of DRAM. The V6000 WS makes it possible to double test frequency, which reduces functional test time. Consequently, RA times can be longer than the pattern time-i.e. no longer hidden, but rather exposed-creating the possibility of timeouts, which drag down yields. As test requirements evolve, SmartRA ensures that RA can remain hidden. SmartRA, with its higher performance, reduces the RA time to once again hide within the pattern time, eliminating timeouts between patterns. High throughput and yields are maintained.

Flexibility of an open architecture
SmartRA's design is based on an open architecture. In contrast to proprietary software architectures from other companies, manufacturers can use RA algorithms they define themselves, or use Verigy turnkey RA algorithms. Additionally, by being based upon the long-tester-life V6000 platform, as well as off-the-shelf blade servers, the testing solution will not become obsolete when today's devices do. Manufacturers only pay for what's needed now, while remaining ready to adapt to future needs, all on the same platform.

Cost-effective immediately and as needs change
SmartRA takes advantage of off-the-shelf high-performance blade servers, which are separate from, yet highly integrated with, the core test solution, the V6000 WS. As a result, when more performance is needed, processing power can easily be added, virtually without limits, and without impacting the test cell footprint. With support of up to eight V6000 WS test cells with a single server rack, manufacturers always have the right performance at the lowest cost.

Testers from other companies include the RA processing within the tester architecture. In order to maintain throughput and yields on such systems, customers need to spend considerably more on processing power.


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SmartRA Product Page Image SmartRA for the V6000 WS
Features & Benefits


Feature
Benefit
High RA performance
Delivers enough processing power to keep RA time hidden behind the shorter pattern times of the V6000's scalable parallelism
 
Scalable servers
Matches V6000 hardware platform scalability, including RA support for 1 TD test capability for DRAM wafer sort for each functional test. Scale number of servers without increasing test footprint
 
Open software architecture
Enables use of customized RA software algorithms or those provided by Verigy
 
Turnkey solution
Speeds time-to-market
 
Scan Controller per test site
Accelerates scan, compression, preprocessing, and transfer of fail data for RA and bitmapping
 
Enhanced LANComm
Accelerates data transfer to the RA server farm for analysis and bitmapping