Advantest's Tester-Per-Site architecture utilizes a multi-site controller and multiple APGs that are dynamically configurable to match specific applications and device types. With each successive generation, our Tester-per-Site architecture has increased parallelism, improved performance, and lowered cost-of-test.

Our sixth generation Tester-Per-Site architecture underpins the new V6000 Series with Active Matrix, enabling optimized test of all memory device types (NOR, NAND, DRAM, SRAM, and MCP) for engineering, wafer sort and final test - at the much lower cost of a Flash tester. The architecture coupled with the Active Matrix supports up to 18K I/O pins, scalable power supplies and scalable performance up to 280 MHz/880 Mbps.

A Long History of Tester-Per-Site Architecture Innovations
The first generation Tester-Per-Site architecture debuted in 1996 on the V1300 test system and delivered an innovative feature set - individual test site controller, algorithmic pattern generator (APG), error catch ram (ECR), pin electronics, and programmable power supplies (PPS) - as well as new performance capabilities, including per-site scalability, I/O flexibility and adaptive test, enabling optimized test times resulting in lower cost-of-test.

The V3300, using second generation architecture, doubled the number of pin resources from 512 to 1024 I/O and test speed from 10 to 20 MHz. With each successive generation of the architecture, features and performance have continued to grow.

In 1999, the V4400 offered our third generation Tester-Per-Site architecture, fully integrated and with new system features including water cooling and test head electronics, further increasing performance to 2304 I/O pins and 50 MHz - 100 MHz in mux mode, and enabling high parallelism for all memory devices. The third generation architecture further enabled the easy transfer of test programs developed on low-cost engineering systems onto volume production systems.

The fourth generation of the architecture, launched with the V5000 series in 2003, delivered dynamically configurable multi-site controllers and scalable APGs, doubled available resources and improved performance - to 4608 I/O pins and 100 MHz.

The fifth generation Tester-Per-Site architecture of the V5500, combined with the Programmable Interface Matrix, optimized single-insertion testing of MCPs with multiple memory types (including Flash, DRAM and SRAM) and high parallelism Flash testing. This resulted in industry-leading tester utilization, throughput and lowest cost-of-test. Available pin resources grew more than five times over the previous generation to 24,576 I/O pins.

Tester-Per-Site Architecture Evolution	100KB
Comparison Table of Architecture Generations	56KB