Verigy - V5500

V5500

Highest utilization for single insertion MCP test and breakthrough parallelism for discrete Flash final test, resulting in lowest cost of test

The Verigy V5500 is a complete final test solution that addresses the complex test challenges faced by manufacturers of MCP and discrete Flash memory devices. The V5500 leverages Verigy's industry-leading memory test expertise into final test, continuing the tradition of breakthrough cost-of-test solutions. The tester-per-site architecture of the V5500, combined with the Verigy Programmable Interface Matrix technology, optimizes single insertion testing of MCPs with multiple memory types (including Flash, DRAM and SRAM) resulting in industry leading tester utilization and throughput.

With the V5500, manufacturers of single- and multi-memory devices reap considerable savings relative to capital investment, consumable expenses, test time reduction, floor space and reliability, over traditional multi-insertion or other high pin count testing alternatives.

The V5500 also provides unmatched parallelism for testing discrete NAND and NOR Flash devices at final test. When set to High Parallelism mode, the Matrix enables testing of x320 NAND and x768 NOR devices to fully utilize today's leading edge handlers.

The V5500 is designed to meet today's and tomorrow's MCP and high-parallelism final test challenges head-on.

V5500 Matrix Demo vid_icon

Product Overview acro_icon 1.79MB

V5500 Test System

Features & Benefits

Key Specifications

Feature

Benefit

Up to 16,384 pins with optional Matrix and 4,096 pins in a single test head		High parallelism enables x320 NAND, x768 NOR and x256 MCP parallelism with optional Programmable Interface Matrix. The optional Matrix's High Parallelism mode is ready for x512 handlers and will enable future testing of more than 1,000 low pin-count devices in parallel.

Programmable Interface Matrix		Two selectable modes in one solution. MCP mode enables single insertion testing at an unparalleled low cost-of-test. High Parallelism mode for discrete Flash enables up to 4x parallelism.

Tester-Per-Site architecture		Enables greater flexibility for tester resource shifting and utilization using the optional Programmable Interface Matrix. Offers the capability to test NAND, NOR, SRAM and DRAM memories. Up to four APGs, 128 shiftable I/Os, and 12 independent power supplies per 512 Matrix pins.

True x320 parallelism test cell		Delivers a complete final test cell solution for customers wanting to take advantage of greater than x256 parallelism testing of packaged Flash and MCPs.

MCP enhanced Versatest software		Provides "multiple die in a stack" flow management for MCP test. Enables quick reuse and integration of existing single die test flows in MCP device testing.

100 MHz / 200Mbps @ 650ps OTA		Higher system performance and accuracy for at-speed testing of packaged devices.

V5000E Engineering Workstation (EWS)		The EWS enables quick prototyping of final test devices with real hardware. Optional single site Matrix is available for MCP and high parallelism engineering development. Provides a complete final test solution from engineering to high volume manufacturing.

Specification

Value

General Characteristics
Maximum number of independent sites per system		128 sites with 32 pins each 64 sites with 64 pins each 32 sites with 128 pins each

Maximum data rate		100 MHz / 200 Mbps

Test Capability
Memory		Dynamic algorithmic pattern generator (APG) Firmware configurable 50 MHz Quad APG and 100 MHz Dual APG modes

Logic		Vector memory (VM)

Embedded Memory		APG / VM

Applications		Final test of discrete and multi-chip package devices (MCP) with NOR and NAND Flash, Mask ROM, Synchronous Flash, SRAM, EEPROM, EPROM, FPGA, EPLD, DRAM and microcontrollers