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V5400

Lowest cost of testing Flash with the flexibility to test DRAM, SRAM and stacked memory devices

For traditional manufacturers of NOR and NAND Flash devices, the V5400 offers a dramatic reduction in the Cost-of-Test for Flash wafer sort. It also provides increased parallelism and configuration flexibility for manufacturers who must test an increasingly complex mix of memory devices. The V5400 is designed to meet all of today's memory test challenges head-on: it has the ability to test Flash, DRAM, SRAM and stacked memory devices; it offers greater parallelism with up to 4608 I/O channels; and it has the flexibility to be configured with up to 144 sites per system.

Continues to lower the cost of memory test
Flexible architecture tests a wide a mix of memory devices
Single platform performs both wafer test and final test

Technical Specifications acro_icon

3.76MB (requires login)

V5400 Test System

Features & Benefits

Feature

Benefit

Highest density test head on the market with 4608 I/O channels		Enables paralleling testing of up to 288 NAND devices (x2 testing) at a significantly lower Cost-of-Test.

Flexible test architecture with Dynamic APG		Tests full-pin-count NOR, low-pin-count NOR, NAND, Synch-Flash, DRAM, and embedded and stacked memory Allows both wafer sort and final test on the same system

50/100 MHz performance with test modes available up to 200 MHz		Greater than value-line performance at value-line pricing, while maintaining the ability to test the full spectrum of memory devices.

Single, scalable platform architecture		Ensures highest hardware and software compatibility and portability from engineering development to high-volume production

Zero Insertion Force (ZIF) interface		ZIF connectors provide higher reliability and repeatability than traditional pogo pin interfaces and enable technology for V5400's 4608 I/O pins (the industry's highest density test head).

Third-generation liquid cooling		Improved thermal stability and MTBF