Fastest memory at-speed final test solution of ultra high-speed GDDR5 and XDR, scalable to 8Gbps with superior throughput, yield and lowest test cost
The Verigy V93000 HSM6800 is the fastest memory solution available today, providing scalable performance to 8.0Gbps and superior throughput and yield for low-cost volume production test of ultra high-speed memory devices, including GDDR5 and XDR.
At-speed final test, scalable to 8Gbps
The HSM6800, targeted for volume production test of ultra high-speed memories, offers native 6.8Gbps at-speed I/O and at-speed memory core access testing up to 64-sites GDDR5 in parallel as well as superior accuracy for best device quality and manufacturing yields.
With its unique twin strobe double clocking feature, the maximum test speed can be scaled to an industry leading 8.0Gbps per pin, addressing the future speeds of all available ultra high-speed memory technologies.
Superior throughput and yield for lowest cost of test
The unmatched native speed headroom of the HSM6800, with its unique 8Gbps twin strobe double clocking feature, provides true 64-sites GDDR5 parallel test capability over the full speed range without the typical throughput penalties of traditional double clocking or pin-muxing implementations, attempting to increase the native ATE speed limits. The resulting benefit is an industry leading throughput and yield for up to 2x good devices per hour and lowest cost of test.
Product Overview 
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64-sites GDDR5 and XDR at single pass
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Avoids "double clocking" or "pin muxing", provides up to 100% throughput advantage for test speeds beyond 4.0Gbps as well as best test coverage and yield for best-in-class cost of test. | |
Memory ATE per-pin
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Fully parallel pattern execution, DC tests and eye-width measurements for best multi-site efficiency. Up to 20% throughput advantage resulting in lowest cost-of-test. | |
| Simultaneous Bi-directional (SBD) | At-speed test of I/O pins on a single transmission line without data bus collisions. Full at-speed test coverage, shortest test-times (no padding), lowest cost-of test. | |
Complete feature-set:
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Ability to test all high-speed failure mechanisms and to ensure high-speed signal integrity Highest test-coverage and yield. | |
| Per-pin timing | Recovery of timing margins for highest yields. | |
| Lowest Timing Jitter and lowest skew | Repeatable, reliable and accurate timing test for highest yields | |
| Most Flexible pin electronics, highest bandwidth | Flexibility to address all high-speed memory technologies. Investment protection | |
Programmable at-speed APG per-pin
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Enables most complex memory test patterns for any fault algorithm to ensure required test quality and fast yield learning. Ready to test advanced I/O capabilities of current and next generation memory architectures. |
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| Maximum Test Speed | 8.0Gbps (6.8Gbps native) | |
| Example Parallelism | 64-sites GDDR5 256-sites DDR3 |
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| Special Functions: | Simultaneous Bi-directional (SBD) Real-Time Strobe Adaptation Embedded Search Support Programmable Signal Equalization Jitter Injection & Measurement CRC Data Generation ABI / DBI Support |
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