The Verigy V93000 HSM3G is the only test solution available today for low-cost volume production of DDR3, DDR4 and beyond. HSM3G offers highly accurate at-speed testing and is scalable to 2.9Gbps. A multi-generation growth path via economical upgrades up to 6.8Gbps date rate provides a unique lifetime value and outstanding return of investment.

Lowest cost of test for mainstream DDR3 & DDR4 up to 2.9Gbps
HSM3G provides highly accurate at-speed I/O and at-speed core access test scalable up to 2.9Gbps, covering the entire DDR3 generation and at least the first two future mainstream speed bins that are expected for DDR4, which are 2.133 Gbps and 2.667 Gbps.

HSM3G achieves native 2.9Gbps data rate, without pin-muxing or double clocking, which guarantees true 256-sites parallel test over the entire speed range without test-time penalties and without compromises to accuracy, functionality, test coverage or yield.

Due to its inherently superior memory ATE per-pin throughput, the V93000 HSM3G provides test-time savings of up to 20 percent. It delivers fully parallel pattern execution, as well as fully parallel DC tests and eye-width measurements, which enables the industry’s best multi-site efficiency. Combined with a competitive price point, the V93000 HSM3G test system provides lowest cost of test for the targeted DRAM speed classes.

Multi-generation test platform with 10 year lifetime via economical upgrades
A unique benefit of the V93000 HSM3G is its future-ready upgradeability to HSM4000 and HSM6800, which gives access to data rates even beyond those of the DDR3/4 generation, featuring investment protection for DDR3, DDR4 and future mainstream DRAM technologies. This ensures more than 10 years of cutting-edge lifetime value over at least three mainstream DRAM device generations and unmatched long-term test economics for outstanding return on investment.

The V93000 HSM platform is future-ready in terms of speed and functionality, offering the most complete feature-set available on the high-speed memory test market. Its programmable at-speed APG per-pin with support for data bus inversion (DBI) and cyclic redundancy check (CRC) data generation enables to test the advanced memory technology features, ensuring best test quality and yield even for the future DDR4 main memory standard.