Verigy - HSM3600

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HSM3600

Fastest memory ATE solution offers at-speed IO and at-speed core test for new class of high-speed DRAMs

The Verigy V93000 HSM Series—the fastest DRAM tester available—is targeted at final test of high-speed memories offering 3.6Gbps at-speed IO and at-speed memory core test to ensure the required test quality and fast yield learning at competitive cost-of-test.

It offers dedicated features for XDR and GDDR but also the flexibility to address all future DRAM technologies ensuring investment protection.

Ensured quality and fast yield learning
Manufacturing Flexibility and Investment Protection
Low technical risk, Proven Architecture for Speed & Accuracy
Highest Manufacturing Yields
Lowest Test Time
Cost competitive, high parallelism solution for targeted speed class

HSM3600

Features & Benefits

Key Specifications

Feature

Benefit

3.6Gbps APG and IO Data Rate		Allowing at-speed test for required quality and fast field learning

At-speed failure capture per-site and Bit-Fail-Map (BFM)		At-speed capture of failure data at all sites in parallel to enable yield learning in production, without extra hardware cost

Most Flexible pin electronics / True differential, low swing signaling, highest bandwidth		Flexibility in manufacturing to address all DRAM/SRAM technologies. Investment protection

Non-interleaved, at-speed per-pin APG, including refresh		Offers most complex memory test patterns to ensure required test quality and fast yield learning

C++ based Memory Test Language		Easy to understand APG programs, rather than register level programming

Source Synchronous		Recovery of timing margins for higher yields. Support of GDDR standard

Per-pin timing and parallel eye-finding		Recovery of timing margins for higher yields. Support of XDR standard

3.6Gbps test at single pass/strobe		Lowest test time. Avoids “double clocking” with its 50% test time penalty

16x sites parallelism for 32x organized GDDR, single test-head		Best parallelism and highest efficiency in this speed class resulting in best cost-of-test

Specification

Value

Data Rate		3.6Gbps data rate (>3.6Gbps with double clocking method) 2.2Gbps data rate (speed-binned HW version)

Non-Interleaved APG Rate		3.6Gbps, per-pin

APG		64 bits addresses in any combination of X,Y and Z Unlimited data bus width (limited by channels / site)

Logic Vector Memory		4MByte per-pin

APG/Failure Memory		12/56MByte per-pin

Pin Electronics		Single-Ended, Differential

Min Swing		50mV

Timing Resolution		1ps

Timing Accuracy		+/- 48ps single-ended pin / differential pair EPA

Timing Skew		+/- 10ps at the device socket; after focus calibration

Special Functions		Source Synchronous (GDDR) and Eye-Finding (XDR)

Site count		16 sites (for x32 organized GDDR and x16 organized XDR)

Max pin-count		1920 pins

Test-Heads		Single Test-Head