HSM2200
High-speed DRAM test system for the economic production of DDR3 SDRAM and beyond, offering a 10-year cutting-edge lifetime value and outstanding ROI
High-speed DRAM test system for the economic production of DDR3 SDRAM and beyond, offering a 10-year cutting-edge lifetime value and outstanding ROI
The new V93000 HSM2200 is the only test solution available today for low-cost mass production of DDR3 SDRAM and beyond. It offers highly accurate at-speed I/O and at-speed memory core access testing of up to 2.2Gbps, future-ready upgradeability to higher data rates and higher parallel test capabilities for unique lifetime value and return on investment.
HSM2200 Features & Benefits
Key Specifications
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| 2.2Gbps APG and I/O Data Rate | Allowing at-speed test for ensured device quality, highest revenue from yield due to superior speed binning performance and yield of top speed bins, as well as fast yield learning | |
| Future-ready upgradeability to higher data rates | Unique return on investment and lifetime value. | |
| 64x sites parallelism for 8x organized DDR3 in a single test-head; Upgradeable to 128x sites parallelism | Best parallelism and highest efficiency in this speed class resulting in superior cost-of-test | |
| True 2.2Gbps test at single pass/strobe | Avoids "double clocking" or "pin muxing". Lowest test time and best test coverage and yield. | |
| Per-pin timing | Recovery of timing margins for highest yields. | |
| Lowest Timing Jitter and lowest skew | Repeatable, reliable and accurate timing test for highest yields | |
| Most Flexible pin electronics, highest bandwidth | Flexibility in manufacturing to address other DRAM/SRAM technologies. Investment protection | |
| At-speed failure capture per-site and Bit-Fail-Map (BFM) | At-speed capture of failure data at all sites in parallel to enable yield learning in production, without extra hardware cost | |
| Non-interleaved, at-speed per-pin APG, including refresh | Offers most complex memory test patterns to ensure required test quality and fast yield learning | |
| Source Synchronous | Recovery of timing margins for higher yields. |
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| Data Rate | 2.2Gbps, per pin (non-mux) Future-ready upgradeability to higher data rates | |
| APG | At-speed APG up to 2.2Gbps Future-ready upgradeability to higher APG rates 64 bits addresses in any combination of X, Y and Z Unlimited data bus width (limited only by channels / site) |
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| Site Count / Parallelism | 64 sites (for x8 single-ended devices) Future-ready upgradeability to 128 sites |
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| Test-Heads | Single Test-Head | |
| Min Swing | 50mV | |
| Timing Resolution | 1ps | |
| Timing Accuracy | +/- 50 ps EPA (within whole system) | |
| Timing Skew | +/- 25 ps (within whole system) | |
| Special Functions | Source-Synchronous 3rd Level Termination |
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