Zero Foot Print ATE System
The Ocelot ZFP is the Lowest Cost Test System for Complex SOCs
New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. The Ocelot ZFP (Zero Foot Print) is a new member of the Ocelot test system family that uses structural test to deliver the comprehensive fault coverage needed while substantially lowering the cost of test.
Best Test Coverage for New, High Performance SOC Devices
- Extended structural test capabilities
- Most comprehensive AC and DC fault coverage
Lowest Space and Power Requirements
- Zero Foot Print (ZFP) fits within any prober form factor
- Air cooled system requires <2kw power
Faster Production Ramps
- Direct interface with EDA tools from Synopsys, Mentor Graphics, Cadence and others
- Newer and better failure analysis capabilities
Product Overview 
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Ocelot ZFPLower the overall cost of test
The Ocelot ZFP is an optimized part of the Inovys family of structural test systems that reduces test costs beyond just acquision costs in many critical areas. Reduced facility costs: the Ocelot ZFP requires no floor space and uses 1/10 the power of traditional test beyond just acquision costs systems. Reduced maintenance costs: over 5,000 hour MTBF. Reduced engineering costs: automated test programs can be generated in a day.
Push production efficiency to higher levels
The Ocelot test system tests sophisticated ICs more efficiently and cost-effectively than a traditional tester using structural test. Structural testing of complex SoCs requires larger pattern memories, internal delay testing, advanced failure capture and analysis capabilities-all of which traditional, functional testers either lack or are too cost prohibitive. Even speed-related faults are far more effectively detected using AC scan vs. functional testing.
Eliminate the Design to Test Bottleneck
Stylus® is a software operating system that is based on the IEEE1450 standard (STIL). This platform provides a seamless, bidirectional interface between the ATE, EDA and DFT worlds. It can directly read timing and pattern files generated by commercial ATPG and BIST tools from Cadence, Mentor Graphics, Synopsys and others.
- Up to 512 bidirectional I/O pins
- 50MHz data rates
- 400MHz clock channels
- AC Scan dynamic waveform switching
- Free running BIST
- Dynamic Data Matrix™
- Extended scan depths up to 4GV
- Flexible memory remapping
- Up to 64Mv pattern memory per pin
- Up to 32M of capture memory per pin
- Full tester rate data capture
- Fail Capture or Data Record modes
- PMU per 64 pins, switchable to any pin
- -2V to +5V voltage range
- 10µA, 100µA, 1µA and 40µA current ranges
- Frequency measure up to 200MHz
- Standard prober and handler docking interfaces
- Direct probe card docking
- STYLUS® tester operating system