Modern Nanometer Level Device Challenges
One of the biggest challenges in modern nanometer level device design and manufacturing is that “What you see is NOT what you get”. The earliest implementation of Design for Manufacturability was the design rule deck. If a designer followed the design rules, or got a wavier, yield problems were solved in the fab. With the explosion in design rules and the subsequent introduction of Design for Yield guidelines, suddenly the rules were not enough. Now you need to match the design to the fab. Two parts running in the same fab may have vastly different yields, at the same random defect density, simply due to design to fab matching.

Another big challenge has been the shift in the economics. Designing for the 65nm or 45nm nodes is expensive. A lot is riding on the time-to-volume-production and time to-entitlement-yield calculations. It is simply too expensive to miss the market window. DFT based yield enhancement methods or logic bit map techniques allow you too look inside the die. Weather it is a systematic defect due to a process weakness or a parametric sensitivity due to a design weakness most of these problems can be solved either by fab or by the designers. How you chose to solve the problems depends on your access to data and influences the robustness of the final fix.

DFT Case Studies

The Yield Enhancement Application

Definition - Test data may be used to look inside the device for problems that cannot be detected in other ways. These issues may be systematic defects such as litho hot spots due to an electrical effect as opposed to a bridged or broken feature. They may be parametric sensitivities such as Vdd-min/max problems due to weak designs or layouts. They may be invisible random defects due to signal-to-noise issues in sub-wavelength optical inspection. They may be system test failure due to tests escapes. Logic bit map can dramatically reduce the time to actionable results.

Purpose - The real goal is to provide volume analysis of the structural test output to quickly identify problems without creating a special flow or having an adverse impact of test times.

Key Driver - Capabilities: Light weight, high speed DFT analysis tools provide sufficient data to provide statistically meaningful data to analyze and triage the issues on nanometer devices for further analysis by EDA tools, Yield Management Systems or failure analysis techniques. Gathering sufficient data for triage requires interaction with the tester during data capture to reduce the time to collect the data using fault targeted techniques to get to an answer faster that it takes to write the raw data to disk.

Focus - To link the desktop structural "instrument" to design-side tools - simulators, ATPG engines, waveform viewers, and even tools such as static timing analysis and layout viewers. To link to fab tools such as YMS systems without leaking design IP.

New Directions - Current directions are to develop tools to identify patterns and trends in the data by accessing layout and design information.

Yield Learning for the V93000

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DfX Solutions for Yield Learning