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YieldVision
Analysis Software for Systematic and Parametric Yield Learning

YieldVision is a design centric, offline analysis suite that enables real time statistical analysis of electrical defects on product die.

YieldVision is our revolutionary, layout centric, offline analysis suite designed specifically for volume yield analysis of complex SOC devices with advanced structural test.

Link failure data to chip design hierarchy and layout

  • Track and review failures by individual or multiple devices
  • Identify gate-level faults by linking to diagnostic tools from Cadence, Magma, Mentor Graphics, and Synopsys
  • Increase yield by systematically identifying failure distribution
  • View and analyze wafer level data
  • Perform high speed trace of the cone of logic driving the failures of difficult defects such as:
    • Blocked chain defects
    • Vdd min and Vdd max defects
  • View and analyze AC performance data to get a "shmoo at every flip-flop"
  • Import and export defects into YMS/DMS systems as point defects in the industry standard KLARF format

Product Overview  acro_icon 179KB




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 Features & Benefits
 Key Specifications


Feature Benefit
ATPG link Minimize data transfer errors with robust bi-directional links to EDA tools.
   
Complete visualization toolset Immediately see the failure in Structural, Hierarchical, or Physical View. Efficiently map failure to physical defect in Advanced Layout.
   
Fault analysis and localization Detect and diagnose elusive new failure mechanisms in smaller geometries - including blocked scan chains and hold-time faults.
   
Wafer-level debug Accelerate silicon debug by enabling diagnosis at the wafer level and providing volume data learning.
   
Single DUT interface board Faster DUT bring-up time with single interface to design and debug. Use the same interface for production test.
   
SmartTest operating environment Classic SmartTest look and feel means that changes to the production environment are minimal.
   
Leverage V93000 systems Significantly increase the utilization and performance of installed systems; common platform for engineering and production.
   



Import and View Structural Test Data

  • Structural View: By scan-chain structure
  • Hierarchal View: By design architecture
  • Physical View: By physical layout (wafer or die level)
  • Histogram View: Sort by speed

Link to Physical Layout Database

  • Provides defect to layout overlay
  • Trace functions (Fan in, fan out)
  • Generate IP protected trace picture (i.e. Splat)
  • Library element Pareto tool

Track & Filter by Multiple Fail Variables

  • Structural Test: Scan chains, bits in chain, scan patterns, pattern set, etc.
  • Manufacturing: Program rev, lot ID, wafer ID, facility, XY coordinate, etc.
  • Pattern Content: execs, bursts, specs, test IDs., etc.

Powerful GUI for Visual Variables

  • Zoom to any level of detail within View
  • Adjust color thresholds to filter failures by numerical intensity
  • Intuitive displays show complete design data on any hierarchy or bit cell

Interfaces with Leading Tools, Including:

  • Mentor Graphics FastScan™
  • Synopsys TetraMAX™
  • Cadence Encounter™
  • Magma Talus™
  • YMS through KLA Results File (KLARF)
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