FlopPlot™
A suite of software analysis tools that display multiple views of device failures, FlotPlot uniquely links a chip's failure data with its design hierarchy and layout.
New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. FlopPlot is a software analysis tool that displays different views of DFT failures and is the first tool that can link a chip's failure data with its design hierarchy and layout.
Product Overview
240KB
New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. FlopPlot is a software analysis tool that displays different views of DFT failures and is the first tool that can link a chip's failure data with its design hierarchy and layout.
- Interpret and analyze first silicon failure data in minutes
- Link failure data to chip design hierarchy and layout
- Track and review failures by individual or multiple devices
- Identify gate-level faults by linking to diagnostic tools from Mentor Graphics, Synopsys, and Cadence
- Increase yield by systematically identifying failure distribution
Faster analysis of structural test data generated by the -- "Personal Ocelot"
for desktop IC debug, characterization and validation and the "Ocelot" and "Ocelot ZFP" for high-volume manufacturing.
Product Overview
240KB
FlopPlot™Features & Benefits
Key Specifications
Faster Problem Resolution for Complex Designs
Large, complex SOC and ASIC designs can generate immense amounts of failure data, which is nearly impossible to interpret and analyze. FlopPlot was developed to handle this large volume of data and convert it into easy to understand information. FlopPlot contains a powerful software tool suite that enables DFT, Test, and FA professionals to quickly identify and resolve failures in very complex devices. In very large designs with millions of gates, failures are easily interpreted through image enhancement techniques.
ATPG Output Flows Directly to Test System
All commercial ATPG tools generate STIL (IEEE1450 Standard Test Interface Language) files. Stylus™, the Inovys test system OS, loads and executes STIL files directly without additional translation steps. With this information, the test system can attach every failure to a flip-flop and pattern for fast analysis and then link to ATPG diagnostic tools to identify faults down to the gate-level.
Large, complex SOC and ASIC designs can generate immense amounts of failure data, which is nearly impossible to interpret and analyze. FlopPlot was developed to handle this large volume of data and convert it into easy to understand information. FlopPlot contains a powerful software tool suite that enables DFT, Test, and FA professionals to quickly identify and resolve failures in very complex devices. In very large designs with millions of gates, failures are easily interpreted through image enhancement techniques.
ATPG Output Flows Directly to Test System
All commercial ATPG tools generate STIL (IEEE1450 Standard Test Interface Language) files. Stylus™, the Inovys test system OS, loads and executes STIL files directly without additional translation steps. With this information, the test system can attach every failure to a flip-flop and pattern for fast analysis and then link to ATPG diagnostic tools to identify faults down to the gate-level.
Import and View Structural Test Data
- Structural view: By scan-chain structure
- Hierarchal view: By design architecture
- Physical view: By physical layout
Track & Filter by Multiple Fail Variables
- Structural Test: Scan chains, bits in chain, scan patterns, pattern set, etc.
- Manufacturing: Program rev, lot ID, wafer ID, facility, XY coordinate, etc.
- Pattern content: Execs, bursts, specs, test IDs, etc.
Powerful GUI for Visual Variables
- Zoom to any level of detail wihin Veiw
- Adjust color thresholds to filter failures by numerical intensity
- Intuitive displays show complete design data on any hierarchy or bit cell
Direct Links with Leading ATPG Tools, including:
- Mentor Graphics FastScan™
- Synopsys TetraMAX™
- Cadence Encounter™
PC-Based with UNIX Links
- Inovys DiagLink™ connects FlopPlot to UNIX-based ATPGs
- Automated scripts enable remote management of long diagnostic jobs via CygWin interface
- Runs on any Win2K or WinXP PC
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