Structural Test Development Overview
Just a few years ago several manufacturers began making optimized structural testers that were more geared to processing Scan and BIST data and operations, as opposed to complex functional sequences. By doing this, the requirements on the ATE were significantly reduced and this in turn reduced the cost associated with the creation of the tester. The market that supports Scan and BIST techniques uses automatic test pattern generation (ATPG) and design-for-test (DFT) techniques to increase the quality metric and to reduce the time-to vectors.
DFT Case Studies
The Production Test Application
Definition - The traditional use of a tester on a production test floor (or as part of the traditional production test flow). Operations Management is responsible for keeping the test floor fully engaged (no idle capacity) and for keeping operating costs low.
Purpose - The same as the traditional purpose of using the tester as a wafer probe tester, final package tester, or multi-site tester (and related processes such as 24 hour burn-in). And along with this purpose, comes all of the standard production concerns about uptime-downtime, throughput, capacity, cost and hardware equipment interfaces (such as handlers and probers).
Key Drivers - Sustained throughput and managed cost.
Focus - Insertion management: Restrictions placed on wafer probe, due to the probe needles, probe head cost, and power problems, line up remarkably with the abilities of structural test. For example, DC, AC and compressed scan vectors, and memory BIST, can be applied through a smaller interface, no high speed signals are required, and the AC testing can be done with a slower data rate applied at the pins -- the internal embedded chip's PLL is used to generate the internal at-speed conditions. If a DFT technique such as wrap-IO has been applied (to allow input pins to be ignored), then a high quality probe insertion can be accomplished by having probe needles touch only a few pins - and with signal requirements well within the electrical capabilities of those needles. This opens the technological door for conducting wider multi-site testing of logic.
New Directions - "Insertion management" on die that contains analog/mixed signal, high-speed IO, embedded flash memory, and other non-digital functions – the old thinking was to have one fully capable machine to do all testing in as few insertions as possible. However, many of the new SOC devices have very low ASPs and conducting multiple insertions on lower cost equipment is proving to be a viable solution. Another new direction in the production space is the use of loadboard solutions for high-speed IO and separate instrumentation for RF testing. Both of these steps enable low cost structural testers to be used in conjunction with these tasks.
A significant new direction is to leverage structural test to identify substantially richer failure information for faster yield improvements.
DfX Solutions for Production Test
- DfX Software and OS - Visually Identify and Diagnose IC Faults Faster