Personal Ocelot
The Fastest Way to Isolate Silicon Problems
The Fastest Way to Isolate Silicon Problems
The Personal Ocelot is the first validation system for semiconductor IC development, debug and failure analysis that fits on an engineer's desk.
New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on efficient test systems. The Personal Ocelot is the first effective desktop validation system for semiconductor IC development. Now verification, product and test engineers can refine and release their engineering samples and test codes from their office or lab. It offers extensive capabilities for testing complex IC devices including ATPG-based scan and BIST that incorporate DFT.
- Debug and structurally validate first silicon in minutes
- Slice weeks from production test program development
- Quickly characterize frequency performance with AC Scan
- Most comprehensive desktop system for silicon validation
Product Overview 
129KB
Personal Ocelot Features & Benefits
Key Specifications
Faster Debug and Validation of Engineering Samples
Now you can use scan test to track silicon failures back to individual flipflops, instead of getting the cycle and pin of the first failure. The Personal Ocelot operating system is designed to support STIL and uses STIL-based files unchanged (like the ATPG output from Cadence Encounter, Mentor Graphics FastScan, and Synopsys TetraMAX). Since these files contain all the necessary flipflop names and chain links of the device's scan chains, the Personal Ocelot can immediately identify failing flipflop and pattern failures.
Faster Production Test Program Development
The Personal Ocelot can quickly develop vectors and test programs without taking a production tester offline. Because the Personal Ocelot and the Ocelot use the same operating system, they can use the same program development and characterization tools. The Personal Ocelot can also debug and diagnose chips that have failed on a production tester. Time can also be significantly reduced to track yield impacts such as erroneous masks, load boards, test environment setting and improper or varying process parameters or defect content.
Quickly Isolate Speed Defects Using AC Scan
The Personal Ocelot's High Performance Clock Channels allow you to perform AC testing to 400MHz (or even higher when internal PLL's are used during scan capture cycles). Transition Delay and Path Delay patterns can be used in conjunction with the Personal Ocelot's evaluation tools to quickly isolate areas where speed performance is a problem.
Eliminate the Design to Test Bottleneck
Stylus® is a software operating system that is based on the IEEE1450 standard (STIL). This platform provides a seamless, bidirectional interface between the ATE, EDA and DFT worlds. It can directly read timing and pattern files generated by commercial ATPG and BIST tools from Cadence, Mentor Graphics, Synopsys and others.
Now you can use scan test to track silicon failures back to individual flipflops, instead of getting the cycle and pin of the first failure. The Personal Ocelot operating system is designed to support STIL and uses STIL-based files unchanged (like the ATPG output from Cadence Encounter, Mentor Graphics FastScan, and Synopsys TetraMAX). Since these files contain all the necessary flipflop names and chain links of the device's scan chains, the Personal Ocelot can immediately identify failing flipflop and pattern failures.
Faster Production Test Program Development
The Personal Ocelot can quickly develop vectors and test programs without taking a production tester offline. Because the Personal Ocelot and the Ocelot use the same operating system, they can use the same program development and characterization tools. The Personal Ocelot can also debug and diagnose chips that have failed on a production tester. Time can also be significantly reduced to track yield impacts such as erroneous masks, load boards, test environment setting and improper or varying process parameters or defect content.
Quickly Isolate Speed Defects Using AC Scan
The Personal Ocelot's High Performance Clock Channels allow you to perform AC testing to 400MHz (or even higher when internal PLL's are used during scan capture cycles). Transition Delay and Path Delay patterns can be used in conjunction with the Personal Ocelot's evaluation tools to quickly isolate areas where speed performance is a problem.
Eliminate the Design to Test Bottleneck
Stylus® is a software operating system that is based on the IEEE1450 standard (STIL). This platform provides a seamless, bidirectional interface between the ATE, EDA and DFT worlds. It can directly read timing and pattern files generated by commercial ATPG and BIST tools from Cadence, Mentor Graphics, Synopsys and others.
- Up to 256 bidirectional I/O pins
- 50MHz data rates
- 400MHz high performance clock channels
- Dynamic waveform switching for AC Scan applications
- Free running mode for BIST applications
- Advanced Pattern Memory Architecture
- Up to 64Mv pattern memory per pin
- Dynamic Data Matrix™
- Flexible memory remapping
- Extends scan depths up to 4GV
- Up to 32M of capture memory per pin
- Full tester rate data capture
- Fail Capture or Data Record modes
- PMU per 64 pins, switchable to any pin
- Frequency measure up to 200MHz
- Standard DPS: Four 2.5A, 0 to 6V channels
- Optional Power Resource Group adds:
- One 5A and three 2.5A channels
- Eight 0.2A, 0 to 16V channels
- Current measure and programmable current limits
- Uses external PC running Windows XP
- USB tester interface
- STYLUS® tester operating system
- Based on STIL (IEEE 1450)
- Comprehensive suite of interactive analysis and debug tools
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