Pin Scale Digital Cards

Consumer demand for more capability and connectivity in a single product is driving the need for more functionality, faster processing and higher speed interfaces in next-generation System-on-a-Chip (SOC) and System-in-Package (SIP) devices. To test these devices, a test system must have the capability to address a range of performance challenges: structural test requirements, rising processing speeds for logic cores, different interfaces and more. And this must all be done at a lower costof-test than last year because of ongoing price erosion. An uncertain future demands the ability to upgrade quickly to meet the next performance challenge while continuing to reduce cost-of-test.

Product Information

Pin Scale 800 acro_icon  1.35MB
Pin Scale 3600 acro_icon  588KB
Pin Scale HX acro_icon  223KB



Technical Specifications

Pin Scale 400 acro_icon  298KB (requires login)
Pin Scale 800 acro_icon  272KB (requires login)
Pin Scale 3600 acro_icon  330KB (requires login)
Power Supplies acro_icon  129KB (requires login)
Infrastructure acro_icon  118KB (requires login)





pin_scale_combo_sm
zoom Pin Scale Digital Cards
 Overview
Features & Benefits 




Product
Max. Data
Rate (Mbps)
Clock Rate (MHz)
EPA/OTA (ps)
Max. Memory
per-pin (MB)
Per Pin License
Options (speed)
Per Pin License
Options (memory)
 
   
Pin Scale 400
> 533 at 1V
> 266 at 1V
200/400
64
DC
100 Mbps
200 Mbps
400+ Mbps
2MB
8MB
16MB
32MB
56MB
 
   
Pin Scale 800
800 a 1V
400 at 1V
175/350
64
200 at 1V
400 at 1V
800 at 1V
8MB
16MB
32MB
64MB
Pin Scale 3600
3600
(characteristic)
1.8 GHz
(characteristic)
30/36
(typical pin)
64
800
1800
3600
8MB
16MB
32MB
64MB
 
   
Pin Scale HX
12800
6400
15 (per pin differential)
64 x 4
(multiplex function)
6.4G
8G *
12.8G *
requires PS3600
as driving card

 * loop mode    * pattern mode





Feature Benefit
Per pin scalability from 200 Mbps to 3.6 Gbps   The test system can be configured to match device requirements, pin-by-pin, for lowest cost.   Permits testing a wide range of interfaces including DDR, G-DDR, PCI Express, S-ATA, HyperTransport and Front Side Bus.
     
256 waveforms   In order to satisfy complex timing needs, 256 waveforms are required. Testing in higher x-modes means that more logical vector memory is available.
     
Unified memory approach   The entire amount of purchased memory is available for both test vectors and sequencer instructions for maximum flexibility. 
     
Test Processor-Per-Pin architecture   Localizing all test processing instead of using centralized resources results in minimal measurement overhead and higher throughput.