Consumer demand for more capability and connectivity in a single product is driving the need for more functionality, faster processing and higher speed interfaces in next-generation System-on-a-Chip (SOC) and System-in-Package (SIP) devices. To test these devices, a test system must have the capability to address a range of performance challenges: structural test requirements, rising processing speeds for logic cores, different interfaces and more. And this must all be done at a lower costof-test than last year because of ongoing price erosion. An uncertain future demands the ability to upgrade quickly to meet the next performance challenge while continuing to reduce cost-of-test.
Product Information
| Pin Scale 800 | 1.35MB |
| Pin Scale 3600 | 588KB |
| Pin Scale HX | 223KB |
Technical Specifications
| Pin Scale 400 | 298KB (requires login) |
| Pin Scale 800 | 272KB (requires login) |
| Pin Scale 3600 | 330KB (requires login) |
| Power Supplies | 129KB (requires login) |
| Infrastructure | 118KB (requires login) |
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| Per pin scalability from 200 Mbps to 3.6 Gbps | The test system can be configured to match device requirements, pin-by-pin, for lowest cost. Permits testing a wide range of interfaces including DDR, G-DDR, PCI Express, S-ATA, HyperTransport and Front Side Bus. | |
| 256 waveforms | In order to satisfy complex timing needs, 256 waveforms are required. Testing in higher x-modes means that more logical vector memory is available. | |
| Unified memory approach | The entire amount of purchased memory is available for both test vectors and sequencer instructions for maximum flexibility. | |
| Test Processor-Per-Pin architecture | Localizing all test processing instead of using centralized resources results in minimal measurement overhead and higher throughput. |