Rapidly detect, diagnose and visualize electrical failures on complex SOC devices shortening time to debug, ramp and volume production.
- Accelerate the time for defect detection and diagnosis by efficient mapping of electrical failures to physical defects using logic bitmaps.
- Uniquely find certain elusive defects while the device is on the tester.
- Enable efficient collaboration between design and test through an integrated toolset.
- Improve productivity and utilization of installed V93000 systems.
- Leverage key learnings from best-in-class industry techniques and methods in a standard toolset and test program development
The Silicon Debug Solution is a suite of tools that provides a comprehensive solution that decreases the time previously needed for defect detection and diagnosis by efficiently mapping electrical failures to physical defects through logic bitmaps. The Silicon Debug solution uniquely finds certain previously elusive faults while complex SOC devices are still on the tester. The solution enables the ability to efficiently collaborate between design and test through an integrated toolset. It also successfully leverages multiple key learnings obtained from best-in-class industry techniques and methods and consolidates them in a standard toolset and test program development.
Solution Overview 
252.25KB
Silicon DebugFaultInsyte provides high-speed automated localization and analysis of hard to find faults such as blocked chains and hold-time faults (Vddmin problems) in chains.
New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. The Silicon Debug solution combines the revolutionary Inovys FaultInsyte software with the Verigy V93000 SOC test system to display structural, hierarchical and physical views of DfT failures. It is the first tool that can link a chip's failure data with its design hierarchy and layout. These capabilities allow the analyst to interpret first silicon data in minutes.
- Structural View: By scan-chain structure
- Hierarchal View: By design architecture
- Physical View: By physical layout (wafer or die level)
- Histogram View: Sort by speed
- Provides defect-to-layout overlay
- Trace functions (fan in, fan out)
- Generate IP-protected trace picture (i.e., Splat)
- Structural test: scan chains, bits in chain, scan patterns, pattern set, etc.
- Manufacturing: program revision, lot ID, wafer ID, facility, XY coordinate, etc.
- Pattern content: execs, bursts, specifications, test IDs, etc.
- Zoom to any level of detail within view
- Adjust color thresholds to filter failures by numerical intensity
- Intuitive displays show complete design data on any hierarchy or bit cell
Works with Verigy V93000 Pin Scale systems.