| Volume yield ananalysis tools |
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Multi-wafer or multi-lot analysis tools including trending and visualization tools. |
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| Improvement to tester- centric pin and cycle count format |
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On-tester conversion to pattern, chain and bit
– In the language of the designer
– In a design hierarchy context
– With accurate x, y die coordinates
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| Layout extraction |
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Lightweight net trace from failing flip-flop providing cell and routing level visualization of failures |
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High-speed, on-tester solution for determining chain faults
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On-the-tester adaptive pattern creation for chain failure localization to chain and bit
– For blocked chains
– For hold-time (Vdd min/max) faults |
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| Adaptive sampling for statistically valid data collection |
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Automated control of sample rates with smart triggers allow user defined data collection for efficient collection of the data that you need. |
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| Protection for design IP |
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IP Protected Splats
– Client-server type interface to allow communication between the fabless company and the foundry that provides enough information to solve the problem without compromising IP |
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| Link to EDA tools |
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Import/export solution to EDA tools from Cadence, Mentor Graphics and Synopsys |
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| Ease of use |
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Award-winning graphical user interface (GUI) that allows any design for test (DFT), failure analysis (FA) or design engineer to say, "I can use it myself!" |
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| Separates visible and non-visible defects |
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Performs KLARF import and overlay to electrical faults. Performs KLARF export to DMS/YMS tools. |
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| Accuracy, stability, repeatability and reliability, flexibility and scalability |
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Proven V93000 architecture delivers |