High-performance, multi-site functional testing now possible at wafer probe
Verigy’s V93000 Direct-ProbeTM solution reduces the length and number of signal path transitions between tester and probe card enabling the industry's highest test performance to now be brought to wireless, WLCSP, MPU and GPU devices at wafer probe.
Working closely with leading probe card manufacturers, Verigy has successfully overcome traditional barriers to delivering high performance test at wafer probe. Current pogo tower-based wafer prober interfaces degrade signal quality because the signal must pass through multiple transition points and a distance of 4 to 5 inches. Verigy’s Direct-Probe solution places the test head directly down into the prober and interfaces directly with the probe card. By removing the conventional mechanical interface between the wafer and tester, Direct-Probe reduces the length and number of signal-path connections between tester pin electronics and probe points, significantly improving signal integrity for device testing. With higher quality signals, the control and performance needed for accurate simulation and full functional testing of digital, mixed-signal and RF devices directly on the wafer is possible.
Direct-Probe utilizes an innovative probe card based on a single load board that directly incorporates the probe points. The single load board can leverage existing final test designs and can be shared between wafer probe and final test, reducing hardware development time and hardware cost.
Direct-Probe is mechanically designed and engineered for contact force management and with the planarity to support large surfaces and high pin counts at wafer test. The result: excellent mechanical and electrical contact is assured.
With Verigy’s V93000 Direct Probe solution, manufacturers can now take a major step forward toward complete high performance functional testing at wafer probe and significantly lower cost of test.
Direct-Probe Solution Overview
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| Scalable support of digital, mixed-signal and RF devices | Ideal for wireless, WLCSP, MPU and GPU devices; Maximum test resource utilization for greatest return on capital investment | |
| Test head in direct contact with probe card | High-performance signal integrity for functional test at wafer stage | |
| Multi-site (up to 32 site) capability | High parallelism and throughput to lower cost of test | |
| Contact force up to 300KG with superior planarity | Excellent contact quality for large die and high pin count devices | |
Highest performance for high-volume manufacturing, multi-site probe test of digital, mixed-signal and RF devices at wafer stage
V93000 Direct-Probe's superior performance is ideal for multi-site probe test of:
Maximum test resource utilization, high parallelism and high throughput for lowest cost of test
With greater multi-site testing (up to 32 sites based on test configuration), reduced index times (<1s) and faster test times, manufacturers can achieve the high throughput needed to drive down cost of test.
Shorter hardware development time and cost due to innovative probe card design
V93000 Direct-Probe’s innovative probe card design, places the probe assembly directly on the load board, improving test performance and reducing hardware cost and hardware design time from design to production.
High-performance signal integrity from tester pin electronics to probe tip

The current industry standard for wafer prober interface (Pogo Tower) degrades the signal quality because the signal must pass through multiple transition points and a distance of 4 to 5 inches. V93000 Direct-Probe interfaces the test head directly with the probe assembly, reducing the length and number of signal path transitions, maintaining signal integrity.
Mechanically designed for contact force management and planarity to support large surfaces and high pin counts at wafer test
V93000 Direct-Probe addresses all major contacting challenges (pad probe, Flip Chip, TSV and WLCSP) by supporting contact force up to 300 kg and maintaining planarity (1mm over 44,000mm²) for excellent mechanical and electrical contact quality for large die sizes and in high pin count devices such as with MPUs and GPUs.