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Yield Learning Solution
The newly introduced Verigy Yield Learning Solution for the V93000 accelerates time to market and maximizes entitlement yield using the most comprehensive, product-based yield analysis solution in the industry. The solution combines an on-tester pre-analysis module on the V93000 test platform with a layout centric analysis and visualization toolset to provide customers with the ability to efficiently triage large quantities of electrical failures into specific logical faults resulting in fast localization of the root cause physical defects. By seamlessly linking electrical test with physical layout data, the solution enables users to more efficiently identify both visible and non-visible yield loss mechanisms to accelerate time to volume production and entitlement yield.  22 KB. |
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Verigy Semiconductor Test Newsletter
June 2009
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Feature Article
Yield Learning Solution
Technical Note
Introduction to Scan Test - Part 2
Test Methodologies
Mixed Signal Lecture Series: DSP-Based Testing Fundamentals 14 - Finite Impulse Response
Q&A
Functional Vector Files and Special Scan Vector Files
Find out more about Verigy's products and solutions:
SoC/SiP
Design for Test/Yield
High Speed Memory
Memory
Visit the go/semi web page for past issues of go/semi.
This is your newsletter, so if you have suggestions for articles, new content, or want to give us feedback contact us.
Yield Learning Solution
Technical Note
Introduction to Scan Test - Part 2
Test Methodologies
Mixed Signal Lecture Series: DSP-Based Testing Fundamentals 14 - Finite Impulse Response
Q&A
Functional Vector Files and Special Scan Vector Files
Find out more about Verigy's products and solutions:
SoC/SiP
Design for Test/Yield
High Speed Memory
Memory
Visit the go/semi web page for past issues of go/semi.
This is your newsletter, so if you have suggestions for articles, new content, or want to give us feedback contact us.
Feature Article
Technical Note
Introduction to Scan Test - Part 2
This paper gives a short introduction into the basics of scan test. The following topics are covered: design, verification, ATPG, test verification, pattern conversion, and debugging on the ATE. Additionally it is discussed how this knowledge about scan test can help to understand the failures and to obtain analysis results in a more efficient and faster way.
70KB.Test Methodologies
Mixed Signal Lecture Series: DSP-Based Testing Fundamentals 14 - Finite Impulse Response
FIR or finite impulse response is a time domain waveform which can be utilized for digital filtering with convolution mathematics. Filtering by the FFT-IFFT method discussed in a previous article has a restriction that the waveform length should be 2n points. Convolution does not have such restriction so that, if the number of data is not 2n, FIR filtering can be useful. In this article, you will see how to create a FIR simply and how to play filtering. More over FIR can be generated with utilizing IFFT. So this is one of the practical applications of IFFT. In order to check the frequency response, a multi-tone signal is used. You can generate a time-domain waveform by using IFFT in the frequency domain. It is described as an example too. In this article you will see two practical applications of IFFT. 1.8MB.
Q&A
Question: "What are the differences between other functional vector files and special scan vector files?"
News
Verigy's Yield Learning Solution Helps Semiconductor Manufacturers Accelerate Time-to-Market and Maximize Entitlement Yield
Verigy Announces Analyst Event in San Francisco
Other
Technical Articles from past issues of go/semi can be found in the Test Technology Resource Center
The Test Technology Resource Center holds Technical Notes, Technical Papers, Test Methodologies and Q&A.
1.8MB.Q&A
Question: "What are the differences between other functional vector files and special scan vector files?"
Often vectors of scan tests are stored in a different format compared to other functional tests, although basically scan test is like any other functional test: Vector by vector certain values are forced at the inputs and certain values are expected at the outputs. Nevertheless, a special scan test vector format exists – what is the difference? 28KB.
28KB.News
Verigy's Yield Learning Solution Helps Semiconductor Manufacturers Accelerate Time-to-Market and Maximize Entitlement Yield
Verigy Announces Analyst Event in San Francisco
Other
Technical Articles from past issues of go/semi can be found in the Test Technology Resource Center
The Test Technology Resource Center holds Technical Notes, Technical Papers, Test Methodologies and Q&A.
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