Verigy Semiconductor Test Newsletter

July 2009

Feature Article
Introducing the V101

Technical Note
Reducing the peak-to-peak variation of the noise floor

Test Methodologies
Mixed Signal Lecture Series: DSP-Based Testing Fundamentals 15 - Filtering in Frequency Domain







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Feature Article

V101 - The Industry’s Lowest-Cost, Zero-Footprint, 100MHz Test Solution Verigy has introduced the V101, a new low-cost, zero-footprint, 100 MHz Tester-on-Board™ system for wafer sort and final test of today’s most cost-sensitive integrated circuits (ICs) and microcontrollers (MCUs). The V101 addresses the extreme low cost requirements of these devices and intense time-to-market pressures.
Lowers Cost of Test through focused design elements including: 1024 pins, integrated test resources on a single board, reduced power consumption. Reduces Program Development Time and simplifies conversions with easy-to-use STIL-based software. Optimized for Wafer Sort with integrated direct probing design. Cost Effectively Test MCUs and other low-pin count, low-cost devices.

Technical Note
Reducing the peak-to-peak variation of the noise floor with a pseudo video filter for the digitized data
This article introduces the technique to reduce the peak-to-peak variation of the noise floor of the (Fast Fourier Transform) FFT calculation results. This technique keeps the SNR value but reduces the peak-to-peak variation of the noise floor. Therefore, you can find the harmonics or the spurious spectrums that amplitudes are very close to the noise floor without losing noise floor characteristics. You can calculate the SNR or THD value from this result and the calculated SNR or THD value is same as the results calculated by the ordinary method.    480KB.

Test Methodologies

Mixed Signal Lecture Series: DSP-Based Testing Fundamentals 15 - Filtering in Frequency Domain