Registration is now open to attend the industry’s best testing conference, VOICE 2010. During these two days you may exchange information and learn from the most accomplished professionals in the field. Your registration entitles you to all technical sessions and presentations during the show, admissions to the Supplier’s Expo and a copy of the conference proceedings. Additionally you’ll be able to attend the evening event which gives you the opportunity to network with industry peers, while enjoying good food and entertainment. Register now for 20% off!

Follow us on

Follow us on
RSVP to our Facebook Event
Follow us on

Noise figure measurements are essential to ensure that minimal noise is added to the receiver chain of the device. Once additional noise joins the signals, receiver performance will be degraded. In extreme cases, it is no longer possible to distinguish the legitimate signal from the noise. The signal and noise get processed together. Attempts to amplify the signal level, for example, will raise the noise level by an equal amount.

There are two primary techniques used to perform noise figure measurements on these devices with automated test equipment (ATE); Y-Factor and Cold Noise (or Gain) methods. Differences between making measurements on RF-to-RF devices and RF-to-baseband devices are discussed in this article., 108 KB

Memory is important part of SOC/SiP. Today’s devices have a variety of capabilities for controlling, communication, entertainment, etc., and memory supports those capabilities as tempory workspace, program code storage and cache. This paper describes how to test memory with ATE without dedicated hardware for memory test., 244 KB

The current success of smartphones and the relentless trend to reduce cost and add capabilities every year are key drivers in the wireless semiconductor business. Combining various RF technologies into one device along with the desire for multi-site testing can easily increase the RF ATE test fixture port count to a range of 48 and beyond. While a few ATE vendors provide test equipment for this requirement, the question remains on how to manage the interfacing and the test fixture design for high density RF without losing performance. The current interfacing and layout paradigm will undergo a significant change. The RF connectors are moved further away from the DUT to allow easier assembly and debugging, but with higher risk of performance degradation due to loss, crosstalk and interference.

This paper evaluates new hardware and layout techniques, discusses mechanical, performance and crosstalk requirements that need to be applied and describes the consequences this will have for loadboard design. , 1 MB

Recently more and more ADC and DAC are getting employed in high frequency applications such as telecommunication devices and digital consumer audio/video devices. The signal fre-quency is getting so high that the converter devices need high quality sampling clocks and test signals. In this issue, let’s look at the effect of jitters in the sampling clock and the test signal., 353 KB

Mixed Signal Lecture Series: DSP-Based Testing Fundamentals 21 - Trend Removal (Part 1)


News

Verigy Honored with 2009 Hot 100 Product Award for Design-for-Manufacturability Software Solution

Ten Asian Editors to Tour Verigy’s Silicon Valley Operations

Global Unichip Adds Verigy V101 as a Test Solution for Low-Cost, High-Volume Consumer Devices


Other

Technical Articles from past issues of go/semi can be found in the Test Technology Resource Center
The Test Technology Resource Center holds Technical Notes, Technical Papers, Test Methodologies and Q&A.