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Test Methodologies
Mixed Signal Lecture Series: DSP-Based Testing Fundamentals 22 - Trend Removal (Part 2)
If you uploaded waveform data from a DUT ADC or a digitizer, you may have experienced ugly DC offset drift in the waveform and the noise floor of its FFT spectrum was extremely slanted. It can often occur when DC blocking capacitors are provided in the signal path in your DUT board. Following up the last article, these more difficult situations are discussed in this issue. .
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Fundamentals of Vector Signal Analysis
, 1.1 MBFundamentals of Vector Signal Analysis
The purpose of this article is to provide the test engineer with a fundamental understanding of vector network analysis. The article will start by describing the fundamentals of impedance, transmission lines, and loads. It will go on to describe common terms for RF/Microwave device characterization such as return loss, SWR (standing wave ratio), and S-parameters. Other RF fundamentals such as Error Correction and the Smith Chart will also be reviewed., 298 KB.
Frequency/Phase Movement Analysis by Orthogonal Demodulation: Part 2 - PLL Lock-in Trend Analysisby RT-SPU Empowered Digitizer
News
Verigy Reports First Quarter 2010 Financial Results; Year-over-Year Revenue Increase of 56%
Verigy to Present at the Morgan Stanley Technology, Media & Telecom Conference
Verigy to Feature Two Keynote Addresses by NASA Mission Leader and Semiconductor Market Analyst at VOICE 2010 Conference
Other
Technical Articles from past issues of go/semi can be found in the Test Technology Resource Center
The Test Technology Resource Center holds Technical Notes, Technical Papers, Test Methodologies and Q&A.
Privacy Officer, Verigy Ltd., 10100 N. Tantau Avenue, Cupertino, CA 95014
, 298 KB.Frequency/Phase Movement Analysis by Orthogonal Demodulation: Part 2 - PLL Lock-in Trend Analysisby RT-SPU Empowered Digitizer
In a previous issue of go/semi, a PLL lock-in time is characterized with the ODM by using a conventional digitizer. The digitizer “MB-AV8” actually has a real-time signal processor integrated inside. It is very good at the ODM. In this issue, the same PLL application is discussed using the RT-SPU empowered digitizer., 606 KB.
, 606 KB.News
Verigy Reports First Quarter 2010 Financial Results; Year-over-Year Revenue Increase of 56%
Verigy to Present at the Morgan Stanley Technology, Media & Telecom Conference
Verigy to Feature Two Keynote Addresses by NASA Mission Leader and Semiconductor Market Analyst at VOICE 2010 Conference
Other
Technical Articles from past issues of go/semi can be found in the Test Technology Resource Center
The Test Technology Resource Center holds Technical Notes, Technical Papers, Test Methodologies and Q&A.
Privacy Officer, Verigy Ltd., 10100 N. Tantau Avenue, Cupertino, CA 95014