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Test Methodologies
Mixed Signal Lecture Series: DSP-Based Testing – Fundamentals 39: F-matrix Cable Simulation
Feature Articles
Verigy Hosts Series of SOC Technical Seminars in Asia-Pacific
Advantest and Verigy to Present Papers at ITC 2011
Check out the V93000 Smart Scale animation and video on Verigy.com.
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Test Methodologies
The wired LAN 100BASE-T system recommends using specified cables such as the category 5 twisted pair cables. DUT boards for RF or high-speed device testing often employ 50Ω micro-strip lines for routing signals. The signals traveling on these media are more or less deteriorated by the media characteristics. Therefore communication devices are often tested tolerance to the signal degradation such as distortion and jitter. In order to emulate such a mission mode environment, the simplest and the most straightforward method is to employ the real cables, boards and circuits used in the real environment. However, this approach has issues in practicability, reliability, maintainability and so on. The point is to generate mission mode distorted signals. So it is acceptable to generate such signals by simulation. This month's article discusses a procedure to synthesize a distorted waveform by combining the conventional F-matrix of transmission line model and FFT&IFFT method.  3.2 MB
Feature Articles
Verigy Hosts Series of SOC Technical Seminars in Asia-Pacific
To highlight our new V93000 Smart Scale generation, Verigy is hosting a series of seven technical seminars in September throughout the Asia-Pacific region. The capabilities of the new Smart Scale Generation will be demonstrated during the seminars and other SOC topics will be covered as well. Join us to learn more about why we believe the V93000 Smart Scale will continue to set the standard for the next generation of test.
Seminar Dates/Locations/Contacts:
Advantest and Verigy to Present Papers at ITC 2011
Advantest is proud to be a Platinum sponsor of this year’s International Test Conference (ITC), taking place September 18-23 in Anaheim, California. Both Advantest and Verigy representatives will present technical papers during the conference. We will also host a hospitality event on Wednesday, September 21 at 6:00 p.m. in Downtown Disney. For an invitation to this event, please contact your sales representative or email info@advantest.com.
Please also plan to join us for our paper presentations during the technical program:
Tuesday, September 20 – 4:00 p.m. Session
(ATE Feature Set Expansions and Test Cost Reduction)
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3.1 Architecture and Implementation of a Truly Parallel ATE Capable of Measuring Picoampere-level Current
D. Acharyya, K. Miyao, D. Ting, D. Lam, R. Smith, P. Fitzpatrick, B. Buras, Verigy; J. Williamson, White Eagle Consulting
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3.2 Development of an ATE Test Cell for At-Speed Characterization and Production Testing
J. Moreira, Verigy
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3.3 Actual Implementation of Multidomain Test: Further Reduction of Cost-of-Test
M. Ogura, A. Maeda, Y. Takahashi, Verigy Japan
Wednesday, September 21 –Poster Session on Exhibits Floor, 12 noon – 2:00 p.m.
- PO 12 Functional Test Abstraction
Sivaram, Advantest America
Wednesday, September 21 – 2:00 p.m. Session 11
(Taming High-Speed Digital Interfaces > 10 Gbps)
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11.2 Elegant Construction of SSC- implemented Signal by AWG and Organized Undersampling of Wideband Signal
H. Okawara, Verigy Japan
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11.3 Real-Time Testing Method for 16-Gbps 4-PAM Signal Interface
M. Ishida, K. Ichiyama, D. Watanabe, M. Kawabata, T. Okayasu, Advantest
Thursday, September 22 – 10:30 a.m. Session
(Advanced Mixed-Signal Test)
- 16.2 Application of a Continuous-Time Level-Crossing Quantization Method for Timing Noise Measurements
T. Yamaguchi, Advantest Laboratories; M. Soma, University of Washington; T. Aoki, Tohoku University; Y. Furukawa, K. Degawa, Advantest; K. Asada, M. Abbas, S. Komatsu, University of Tokyo
Other
Technical Articles from past issues of go/semi can be found in the Test Technology Resource Center
The Test Technology Resource Center holds Technical Notes, Technical Papers, Test Methodologies and Q&A.
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